1. Field of the Invention
The present invention relates to a hierarchical word line driving circuit for a semiconductor memory device, and in particular to an improved hierarchical word line driving circuit for a semiconductor memory device which can reduce a sub-threshold voltage leakage current because a sub-word line is disabled at a back bias voltage, which can overcome a layout penalty because an additional NMOS transistor for preventing the sub-word line from floating is not employed, and which can sufficiently obtain a line pitch passing above the sub-word line.
2. Description of the Background Art
FIG. 1 is a circuit diagram illustrating a conventional hierarchical word line driving circuit for a semiconductor memory device. As shown therein, the conventional hierarchical word line driving circuit includes a main word line driver 1 and a sub-word line driver 2.
Here, the main word line driver 1 includes: a first PMOS transistor PM11 having its substrate commonly connected to its source to receive a driving voltage VPP; and a first NMOS transistor having its source connected to a ground voltage VSS, and having its substrate connected to receive a back bias voltage VBB, the first PMOS transistor PM11 and the first NMOS transistor NM11 being connected in series between the driving voltage VPP and the ground voltage VSS, having their gates commonly connected to a main word line, and having their drains commonly connected to output an output signal MWLB.
The sub-word line driver 2 includes: a first inverter INV11 inverting a lower coding signal FXB; a second PMOS transistor PM12 having its source connected to receive an inverted signal of the lower coding signal FXB by the first inverter INV11, and having its substrate connected to receive the driving voltage VPP; a second NMOS transistor NM12 having its source connected to the ground voltage VSS, and having its substrate connected to receive the back bias voltage VBB; and a third NMOS transistor NM13 having its source connected to the ground voltage VSS, and having its substrate connected to receive the back bias voltage VBB, the second PMOS transistor PM12 and the second NMOS transistor NM12 having their gates commonly connected to receive the output signal MLWB from the main word line driver 1, the second PMOS transistor PM12 and the second and third NMOS transistors NM12, NM13 having their commonly-connected drains connected to a sub-word line SWL.
Here, the driving voltage VPP is a word line voltage, and the back bias voltage VBB is operated as a well bias of a P-type substrate.
In addition, the main word line signal is a signal receiving upper coding.
The operation of the conventional hierarchical word line driving circuit for the semiconductor memory device will now be described in detail with reference to timing diagrams of FIG. 2.
When it is presumed that one block includes the 64 main word lines MWL controlled according to an upper coding signal, and it is also presumed that 8 lower coding signals FXB are generated, the 8 lower coding signals FXB are assigned to each main word line MWL, and thus total 512 sub-word lines exist in the block.
As illustrated in FIG. 2, in case the main word line MWL and the lower coding signal FXB are precharged with the driving voltage VPP at an initial stage, the driving voltage VPP is applied to the gate of the second NMOS transistor NM12. Accordingly, the sub-word line SWL is discharged to the ground voltage VSS. When the main word line MWL of the block selected by the upper coding signal is transited from the ground voltage VSS to the driving voltage VPP, as shown in FIG. 2(c), the output signal MWLB from the main word line driver 1 is transited from the driving voltage VPP to the ground voltage VSS, and applied to the gate of the second PMOS transistor PM12, thereby turning on the second PMOS transistor PM12.
Thereafter, when the lower coding signal FXB is transited from the driving voltage VPP to the ground voltage VSS, the driving voltage VPP is applied to the source of the second PMQS transistor PM12. At this time, since the gate of the second PMOS transistor PM12 has been already connected to the ground voltage VSS, a voltage between the gate and source of the second PMOS transistor PM12 becomes a minus driving voltage xe2x88x92VPP, and thus the second PMOS transistor PM12 is turned on.
Here, in a state where the output signal MWLB from the main word line driver 1 is enabled to the ground voltage VSS, when the selected lower coding signal FXB is enabled to the ground voltage VSS as shown in FIG. 2(a), the non-selected lower coding signal FXB is disabled to the driving voltage VPP as shown in FIG. 2(b) for preventing the sub-word line connected to the non-selected lower coding signal FXB from floating. As a result, the third NMOS transistor NM13 of the sub-word line driver 2 is turned on, and thus the sub-word line is connected to the ground voltage VSS through the third NMOS transistor NM13.
In the conventional sub-word line driver, when the output signal MWLB from the main word line driver is at a low level VSS and the lower coding signal FXB is at a high level VPP, the voltage between the gate and source of the second PMOS transistor becomes 0V, and thus the sub-word line floats. Accordingly, in order to overcome such a disadvantage, as soon as the lower coding signal FXB is transited to the driving voltage VPP, the non-selected sub-word line is connected to the ground voltage VSS by employing the third NMOS transistor. However, using the third NMOS transistor narrows the pitch of a metal line passing above the sub-word line driver, thus making it more difficult to design the layout. As a result, the layout area and costs of the chip are increased.
Accordingly, it is an object of the present invention to provide a word line driving circuit for a semiconductor memory device which can prevent a sub-word line from floating, without using an additional NMOS transistor.
In order to achieve the above-described object of the present invention, there is provided a word line driving circuit for a semiconductor memory device, including: a main word line driver consisting of a transmission gate for selectively outputting a main word line signal, a selective latch unit for selectively latching and outputting the main word line signal selectively transmitted by the transmission gate, and a level shift unit for outputting an output from the selective latch unit or a back bias voltage according to a block selection signal and the main word line signal; and a sub-word line driver controlled according to an output from the main word line driver, for driving a sub-word line by using an inputted lower coding signal or a ground voltage.